1. Field of the Invention
The present invention relates to the design system of a semiconductor integrated circuit element, a program and a program product for causing a computer to function as the design system, the design method of a semiconductor integrated circuit element, and a semiconductor integrated circuit element.
2. Description of Related Art
With the microfabrication of semiconductor integrated circuits in recent years, measures against the noise of a semiconductor integrated circuit element have become important. Mentioned as a technique for the measures is one wherein a decoupling capacitor is inserted into the power source circuit (between the power source wiring and ground wiring) of the integrated circuit, thereby to stabilize the potentials of the power source circuit and to attain the stable operation and enhanced characteristics of the integrated circuit.
Especially in the integrated circuit in which an analog circuit and a digital circuit are coexistent, it is effective to insert the capacitor between the power source wiring in the analog circuit (power source wiring for the analog circuit) and the ground wiring.
Meanwhile, in designing a semiconductor integrated circuit element, a chip layout is first determined. More specifically, as shown in the flow chart of FIG. 1, an input/output block is arranged at a step S101. Thereafter, the arrangement of analog-signal-circuit blocks which afford functions and characteristics to be achieved by the integrated circuit element, and function blocks such as a CPU core, is determined (step S102). Subsequently, the arrangement of the wiring lines between the input/output block and the analog-signal-circuit blocks is determined (step S103). The wiring lines for transferring analog signals need to be laid in consideration of the influence of noise, and impedance matching, and the parts are sometimes determined by the manual work of a designer. Thereafter, at a step S104, unit cells which are formed of logic circuits such as NAND, NOR, INV and FF are arranged between the function blocks. Further, at a step S105, the wiring lines between the unit cells, between the input/output block and the function blocks, between the function blocks, between the function blocks and the unit cells, etc. are determined. Thus, the arrangement and wiring of the layout pattern of an IC chip is completed.
In case of inserting the capacitor stated above, the capacitor is manually inserted and formed in an open space after the determination of the chip layout or amidst the above layout operations, and the capacitor and the power source wiring are often connected manually. More specifically, as shown in FIG. 1 by way of example, at a step S106, the capacitor is formed in the open space which belongs to neither the input/output block nor the function blocks, such as the interstice between the input/output block and the function block or the interstice between the function blocks, and the capacitor and the power source wiring are connected (step S107), whereby the layout pattern of the IC chip is finished up.
On the other hand, the chip layout has recently been automated, and an automatic layout tool is often employed especially for a large-scale integrated circuit. In case of employing the automatic layout tool in this manner, the arrangement of the capacitor is inevitably done after the completion of the layout as shown in the flow chart of FIG. 1.
Since, however, the arrangement of the input/output block and the function blocks is preferred at the stage of design, the open space in which the capacitor can be formed differs in shape and size variously. It is troublesome and has increased the cost of the design to design and arrange the capacitor manually in adaptation to the open space. Especially when the capacitor is manually arranged after the completion of the layout, a large number of restraints are involved, and long working hours are expended in appropriately arranging the capacitor in the open space so as to ensure a larger capacity. Nevertheless, a demand for shortening a design and development period is making it difficult more and more to secure sufficient working hours. Moreover, since skill is required for the way of arrangement, etc., the electrostatic capacitance of the capacitor obtained is often different depending also upon the degree of skill of an operator, and it is sometimes difficult to appropriately form the capacitor having the large electrostatic capacitance.